MESI protocol
The dominant cache-coherence protocol in modern multicore CPUs, tracking each cache line in one of four states — Modified, Exclusive, Shared, Invalid — to keep cores' views of memory consistent.
MESI is the classic multicore cache-coherence protocol. Every cache line held in any core’s private cache is tagged with one of four states:
- Modified (M) — this core has the only copy, and it has been written; main memory is stale.
- Exclusive (E) — this core has the only copy, but it matches main memory.
- Shared (S) — multiple cores have read-only copies, all matching memory.
- Invalid (I) — the copy is not valid; treat as a miss.
When one core writes a line in Shared state, it must broadcast an invalidation to the other caches and transition to Modified — this is the coherence traffic that shows up under false sharing. When another core reads a line currently in Modified state elsewhere, the owning core forwards the line (HITM — “hit modified”) and the two transition to Shared (or the variant protocol’s Owned state).
Real CPUs extend MESI in practice:
- MESIF (Intel) adds a Forward state to nominate one sharer as the canonical responder for reads, avoiding response storms.
- MOESI (AMD, Arm) adds an Owned state for a dirty line that is also shared, delaying writeback.
The protocol itself is cycle-accurate — you don’t program against it directly. What you program against is its consequences: coherence latency when a line bounces between cores, invalidation storms under false sharing, and the ordering guarantees that memory models (x86-TSO, Arm weak) expose to software. perf c2c is the tool for seeing coherence traffic in practice.